Electronic components such as computers, Personal Digital Assistants (PDAs), cellular telephones, video display and processing devices, and various other electronic systems are now considered essential for day-to-day life and consumers insist that these devices be portable enough to accompany them wherever they go. This places two important demands on the electronics industry: smaller devices and longer battery life. Unfortunately, these two demands are at odds with each other since longer battery life typically means bigger batteries and therefore bigger devices. Other than increasing battery size, the only way to increase battery life is to decrease power consumption. Consequently there is a strong demand in the electronics industry for lower power consumption, which, in turn, allows smaller batteries for the same device operating time.
In addition, the other limiting factor in current electronics design is heat dissipation. Here again, power consumption is central since the key to generating less heat is using less power. Consequently, the minimization of power usage is an important factor in virtually all-new electronic designs and power usage/waste that was considered acceptable in the prior art is no longer being tolerated.
One area where power usage/waste was tolerated in the prior art, mostly because no solution to the power waste was ever offered, is in dynamic flip-flops. Since a significant amount of power in modern electronic devices is used to operate the flip-flops, which can easily number in the thousands and hundreds of thousands in a single device, the power wasted in prior art dynamic flip-flop circuits was non-trivial and a very real concern.
Dynamic flip-flops and their operation are well known to those of skill in the art. Consequently, a detailed discussion of the operation and structure of a specific prior art dynamic flip-flops is not included here to avoid detracting from the present invention. However, a brief summary of the key points of prior art dynamic flip-flops is provided to clarify the structure and advantages of the present invention.
In prior art dynamic flip-flops, dynamic nodes were pre-charged each clock cycle to provide high speed operation once data was captured, i.e., the dynamic node was pre-charged so that once data arrived flop can do evaluation by discharging this node or keeping the charges depending on the incoming data just like the general dynamic logic circuits. Many prior art dynamic flip-flops also included a Clock Enable (CE) function, which made multiple cycle paths possible in digital circuits. When prior art dynamic flip-flops were in a holding mode, i.e., in the clock disable state, prior art dynamic flip-flops kept the previous data from feedback path, i.e., there was no change in the data and there were no output toggles. Using prior art dynamic flip-flops, if previous data was “high”, or a digital one, the prior art dynamic flip-flops kept pre-charging and discharging the internal dynamic node every cycle. However, since the data, by definition, was not changing, significant power was wasted in this pre-charging and discharging the internal dynamic node each cycle. Of course, the more cycles digital “1” was held, the more power was wasted. Consequently, prior art dynamic flip-flops used power unnecessarily.
FIG. 1 shows an exemplary timing diagram 100 for a typical prior art dynamic flip-flop (not shown). An L1 clock signal L1CLK 101 for a typical prior art dynamic flip-flop (not shown) is illustrated on graph 103, a Clock Enable signal CE 111 for a typical prior art dynamic flop-flop (not shown) is illustrated on graph 115, and the voltage 121 on a dynamic node (not shown) of a typical prior art dynamic flip-flop (not shown) is illustrated on graph 125. As seen in FIG. 1, voltage 121 on a dynamic node (not shown) of a typical prior art dynamic flip-flop (not shown) repeatedly charged to pre-charge voltage 127, see points 131, 133, 135, 137, 139, 141 and 143 and discharged to discharge voltage 129, see points 151, 153, 155, 157, 159, 161 and 163. Of particular note is the fact that, in the prior art, pre-charging of a typical prior art dynamic flip-flop (not shown) took place even at points 133, 135, 137 and 139, during period 117, while Clock Enable signal CE 111 was low and when, by definition, the data was not changing. Consequently, significant power was wasted pre-charging to voltage 127 and discharging to voltage 132 the dynamic node each cycle. Consequently, as discussed above, prior art dynamic flip-flops used power unnecessarily.
Since, as noted above, a significant amount of power in modern electronic devices is used to operate the flip-flops, the power wasted in prior art dynamic flip-flop circuits was non-trivial. What is needed is a method and apparatus for avoiding the power waste created by prior art dynamic flip-flops unnecessarily pre-charging and discharging the internal dynamic node.